Lecture 0: Why Superconducting Electronics?

Why Superconducting Electronics? - SCE Futures

Contents¶

1. The Problem: Computing's Energy Crisis
2. The Opportunity: Superconducting Electronics
3. Why AQFP?
4. Where SCE Fits
5. Where SCE Does NOT Fit
6. Open Problems
7. The Path Forward
8. Key Takeaways

!!! abstract "Learning Objectives" - Separate device measurements, cooling assumptions, and full-system energy comparisons. - Explain why gradual AQFP switching dissipates very little energy at the device. - Identify workload properties that favor deeply pipelined superconducting accelerators. - Distinguish measured results, modeled results, and roadmap targets.

In [1]:

# Setup
import matplotlib.pyplot as plt
import matplotlib.patches as patches
from matplotlib.patches import FancyBboxPatch
import numpy as np

COLORS = {
    'primary': '#2196F3',
    'secondary': '#FF9800',
    'success': '#4CAF50',
    'danger': '#f44336',
    'dark': '#1a1a2e',
    'light': '#f5f5f5',
    'purple': '#9C27B0',
    'cyan': '#00BCD4',
    'cmos': '#f44336',
    'sce': '#4CAF50',
}

plt.rcParams['figure.facecolor'] = 'white'
plt.rcParams['axes.facecolor'] = 'white'
plt.rcParams['font.size'] = 11

print("Setup complete.")

# Setup import matplotlib.pyplot as plt import matplotlib.patches as patches from matplotlib.patches import FancyBboxPatch import numpy as np COLORS = { 'primary': '#2196F3', 'secondary': '#FF9800', 'success': '#4CAF50', 'danger': '#f44336', 'dark': '#1a1a2e', 'light': '#f5f5f5', 'purple': '#9C27B0', 'cyan': '#00BCD4', 'cmos': '#f44336', 'sce': '#4CAF50', } plt.rcParams['figure.facecolor'] = 'white' plt.rcParams['axes.facecolor'] = 'white' plt.rcParams['font.size'] = 11 print("Setup complete.")

Setup complete.

---

1. Computing's Energy Constraint¶

---

Useful work is limited by power¶

Modern AI systems turn electrical power into computation, memory traffic, communication, and heat. Increasing transistor count does not guarantee a proportional increase in useful throughput when site power, package power density, memory bandwidth, or cooling capacity becomes the binding constraint.

The end of constant-power scaling¶

Dennard scaling once allowed smaller transistors to switch faster without raising power density. Voltage scaling slowed in the mid-2000s, while leakage and interconnect costs became more important. Architecture, precision, and packaging still improve, but energy per useful operation now requires system-level work rather than a simple shrink.

The question for this course¶

Superconducting electronics starts from a different device-energy scale. The engineering question is whether that headroom survives clock distribution, memory, I/O, cryogenic refrigeration, and finite utilization. Every comparison in this course therefore names both its boundary and its evidence state.

In [2]:

# Modeled wall-energy advantage across cooling assumptions
corners = ['Packaged downside\n5 K / 980 W/W', 'Production\n5 K / 400 W/W', 'Plant upside\n5 K / 207 W/W']
low = np.array([6.4, 11.8, 15.7])
high = np.array([8.5, 14.8, 19.5])
mid = (low + high) / 2
err = np.vstack((mid - low, high - mid))

fig, ax = plt.subplots(figsize=(10, 5))
ax.bar(corners, mid, yerr=err, capsize=7,
       color=[COLORS['secondary'], COLORS['sce'], COLORS['primary']], alpha=0.88)
ax.axhline(1, color=COLORS['dark'], linewidth=1)
ax.set_ylabel('Wall-energy advantage vs host-inclusive B200 (×)')
ax.set_title('AQFP Static-Inclusive System Model')
ax.grid(axis='y', alpha=0.25)
for i, (lo, hi) in enumerate(zip(low, high)):
    ax.text(i, mid[i] + err[1, i] + 0.6, f'{lo:.1f}–{hi:.1f}×', ha='center', fontweight='bold')
plt.tight_layout()
plt.show()

print('Modeled, not measured-system performance.')
print('Comparator: host-inclusive NVIDIA B200, dense FP4, at the wall.')

# Modeled wall-energy advantage across cooling assumptions corners = ['Packaged downside\n5 K / 980 W/W', 'Production\n5 K / 400 W/W', 'Plant upside\n5 K / 207 W/W'] low = np.array([6.4, 11.8, 15.7]) high = np.array([8.5, 14.8, 19.5]) mid = (low + high) / 2 err = np.vstack((mid - low, high - mid)) fig, ax = plt.subplots(figsize=(10, 5)) ax.bar(corners, mid, yerr=err, capsize=7, color=[COLORS['secondary'], COLORS['sce'], COLORS['primary']], alpha=0.88) ax.axhline(1, color=COLORS['dark'], linewidth=1) ax.set_ylabel('Wall-energy advantage vs host-inclusive B200 (×)') ax.set_title('AQFP Static-Inclusive System Model') ax.grid(axis='y', alpha=0.25) for i, (lo, hi) in enumerate(zip(low, high)): ax.text(i, mid[i] + err[1, i] + 0.6, f'{lo:.1f}–{hi:.1f}×', ha='center', fontweight='bold') plt.tight_layout() plt.show() print('Modeled, not measured-system performance.') print('Comparator: host-inclusive NVIDIA B200, dense FP4, at the wall.')

Modeled, not measured-system performance.
Comparator: host-inclusive NVIDIA B200, dense FP4, at the wall.

---

2. A Superconducting Path¶

---

What superconducting electronics changes¶

Below a critical temperature, a superconductor supports DC current without resistive voltage drop. Superconducting circuits still dissipate energy in junctions, dielectrics, clock networks, interfaces, and room-temperature support electronics, so zero wire resistance is a starting point rather than a complete system argument.

AQFP encodes state in the polarity of a circulating superconducting current. Its multiphase AC excitation gradually reshapes each gate's potential landscape; the state follows a moving energy minimum and dissipates very little at the device. The clock also establishes when each pipeline stage evaluates.

Quantitative anchors¶

Quantity	Value	Evidence and boundary
Landauer floor	0.040 zJ per irreversible bit erase	Thermodynamic value at 4.2 K
AQFP reference	1.4 zJ per Josephson junction per cycle	Published measurement of an 8-bit adder at 4.2 K and 5 GHz
Production system model	11.8–14.8× less wall energy	Modeled at 5 K and 400 W/W against a host-inclusive B200, FP4-for-FP4
Packaged downside model	6.4–8.5× less wall energy	Modeled at 5 K and 980 W/W; packaged-machine class, same workload and accounting basis
Plant upside model	15.7–19.5× less wall energy	Modeled at 5 K and 207 W/W; central-helium-plant class, same workload and accounting basis

The device measurement and the system model answer different questions. The system result charges every routed junction each cycle and includes warm memory, I/O, scalar work, static cryostat load, and refrigeration.

Sources: Takeuchi et al., Applied Physics Letters 114, 042602 (2019); system figures use the current AM static-inclusive model, as of 2026-08-13.

In [3]:

# Published device-energy anchor at 4.2 K
labels = ['Landauer floor\n(bit erase)', 'AQFP measurement\n(JJ-cycle)']
energy_zj = [0.040, 1.4]

fig, ax = plt.subplots(figsize=(9, 5))
bars = ax.bar(labels, energy_zj, color=[COLORS['secondary'], COLORS['sce']], width=0.58)
ax.set_yscale('log')
ax.set_ylabel('Energy at 4.2 K (zJ)')
ax.set_title('Thermodynamic Floor and Published AQFP Measurement')
ax.grid(axis='y', which='both', alpha=0.25)
for bar, value in zip(bars, energy_zj):
    ax.text(bar.get_x() + bar.get_width()/2, value * 1.25, f'{value:.3g} zJ', ha='center', fontweight='bold')
plt.tight_layout()
plt.show()

print('1.4 zJ/JJ-cycle: Takeuchi et al., APL 114, 042602 (2019), 4.2 K and 5 GHz.')
print('The 35× ratio is a device-to-thermodynamic-floor comparison, not a system advantage.')

# Published device-energy anchor at 4.2 K labels = ['Landauer floor\n(bit erase)', 'AQFP measurement\n(JJ-cycle)'] energy_zj = [0.040, 1.4] fig, ax = plt.subplots(figsize=(9, 5)) bars = ax.bar(labels, energy_zj, color=[COLORS['secondary'], COLORS['sce']], width=0.58) ax.set_yscale('log') ax.set_ylabel('Energy at 4.2 K (zJ)') ax.set_title('Thermodynamic Floor and Published AQFP Measurement') ax.grid(axis='y', which='both', alpha=0.25) for bar, value in zip(bars, energy_zj): ax.text(bar.get_x() + bar.get_width()/2, value * 1.25, f'{value:.3g} zJ', ha='center', fontweight='bold') plt.tight_layout() plt.show() print('1.4 zJ/JJ-cycle: Takeuchi et al., APL 114, 042602 (2019), 4.2 K and 5 GHz.') print('The 35× ratio is a device-to-thermodynamic-floor comparison, not a system advantage.')

1.4 zJ/JJ-cycle: Takeuchi et al., APL 114, 042602 (2019), 4.2 K and 5 GHz.
The 35× ratio is a device-to-thermodynamic-floor comparison, not a system advantage.

System Architecture¶

An SCE system integrates superconducting chips within a cryogenic environment. Understanding this architecture is essential for grasping the thermal budget constraints:

In [4]:

# Visualize: SCE System Architecture
fig, ax = plt.subplots(figsize=(14, 8))
ax.set_xlim(0, 16)
ax.set_ylim(0, 10)
ax.axis('off')

# Color scheme for temperature zones
colors_temp = {
    '40K': '#ffe0cc',   # orange
    'cold': '#cce5ff',    # cold blue
}

# === CRYOSTAT (center) ===
# Cryostat vacuum vessel (outer boundary) - narrower to leave room for external components
cryostat = FancyBboxPatch((4, 0.5), 7, 9, boxstyle="round,pad=0.05",
                           facecolor='#f0f0f0', edgecolor='black', linewidth=3)
ax.add_patch(cryostat)
ax.text(7.5, 9.7, 'Cryostat (vacuum)', ha='center', fontsize=12, fontweight='bold')

# 40K - Intermediate stage (radiation shield)
stage_40k = FancyBboxPatch((4.5, 1), 6, 7.5, boxstyle="round,pad=0.05",
                            facecolor=colors_temp['40K'], edgecolor='black', linewidth=2)
ax.add_patch(stage_40k)
ax.text(7.5, 8.7, '40K Stage', ha='center', fontsize=10, fontweight='bold')

# Cold stage (innermost): 4 K bench, 5 K production model
stage_4k = FancyBboxPatch((5, 1.5), 5, 6, boxstyle="round,pad=0.05",
                           facecolor=colors_temp['cold'], edgecolor='black', linewidth=2)
ax.add_patch(stage_4k)
ax.text(7.5, 7.7, '4–5 K Stage', ha='center', fontsize=10, fontweight='bold', color=COLORS['primary'])

# SCE chip at the cold stage
chip = FancyBboxPatch((5.5, 3), 4, 3, boxstyle="round,pad=0.02",
                       facecolor=COLORS['sce'], edgecolor='black', linewidth=2, alpha=0.8)
ax.add_patch(chip)
ax.text(7.5, 4.5, 'AQFP\nProcessor', ha='center', va='center', fontsize=12, 
        fontweight='bold', color='white')
ax.text(7.5, 3.2, '~mW dissipation', ha='center', fontsize=9, color='white')

# === COLD HEAD (outside cryostat, connected via flange) ===
cryo_head = FancyBboxPatch((11.5, 3), 1.8, 4, boxstyle="round,pad=0.03",
                            facecolor='#c0c0c0', edgecolor='black', linewidth=2)
ax.add_patch(cryo_head)
ax.text(12.4, 6.3, 'Cold\nHead', ha='center', fontsize=9, fontweight='bold')
ax.text(12.4, 4.5, 'GM/Pulse\nTube', ha='center', fontsize=8)

# Cold finger penetrating into cryostat
ax.plot([11, 11.5], [5, 5], color='#c0c0c0', linewidth=8, solid_capstyle='butt')
ax.plot([11, 11.5], [5, 5], color='black', linewidth=10, solid_capstyle='butt', alpha=0.3)
ax.text(10.5, 5.5, 'Cold\nfinger', fontsize=7, ha='center')

# === COMPRESSOR (external, bottom right) ===
compressor = FancyBboxPatch((12.5, 0.5), 3, 1.8, boxstyle="round,pad=0.02",
                             facecolor='#e0e0e0', edgecolor='black', linewidth=2)
ax.add_patch(compressor)
ax.text(14, 1.4, 'Compressor', ha='center', fontsize=10, fontweight='bold')
ax.text(14, 0.9, '~1-10 kW (room temp)', ha='center', fontsize=8, color=COLORS['danger'])

# Helium lines connecting compressor to cold head
ax.annotate('', xy=(12.4, 2.9), xytext=(13.2, 2.4),
            arrowprops=dict(arrowstyle='-', color='gray', lw=3, 
                          connectionstyle='arc3,rad=-0.2'))
ax.annotate('', xy=(12.4, 3.1), xytext=(14.5, 2.4),
            arrowprops=dict(arrowstyle='-', color='gray', lw=3,
                          connectionstyle='arc3,rad=0.2'))
ax.text(13.8, 2.6, 'He lines', fontsize=7, color='gray')

# === HOST SYSTEM (left side, completely outside cryostat) ===
host = FancyBboxPatch((0.3, 2.5), 2.8, 5, boxstyle="round,pad=0.05",
                       facecolor=COLORS['secondary'], edgecolor='black', linewidth=2, alpha=0.8)
ax.add_patch(host)
ax.text(1.7, 6.8, 'Room Temperature', ha='center', fontsize=10, fontweight='bold')
ax.text(1.7, 5.5, 'Host System', ha='center', fontsize=11, fontweight='bold', color='white')
ax.text(1.7, 4.5, 'CPU / GPU\nMemory\nNetwork', ha='center', fontsize=10, color='white')
ax.text(1.7, 3.0, '300K', ha='center', fontsize=12, fontweight='bold', color='white')

# === I/O CABLES (crossing into cryostat) ===
ax.annotate('', xy=(5.3, 4.8), xytext=(3.2, 4.8),
            arrowprops=dict(arrowstyle='->', color=COLORS['primary'], lw=3))
ax.annotate('', xy=(3.2, 4.2), xytext=(5.3, 4.2),
            arrowprops=dict(arrowstyle='->', color=COLORS['primary'], lw=3))

ax.text(3.6, 5.1, 'Data In', fontsize=9, color=COLORS['primary'], fontweight='bold')
ax.text(3.6, 3.9, 'Data Out', fontsize=9, color=COLORS['primary'], fontweight='bold')

# Feedthrough annotation
ax.text(4.2, 6.2, 'Vacuum\nfeedthrough', fontsize=8, ha='center',
        bbox=dict(boxstyle='round', facecolor='white', edgecolor='gray', alpha=0.9))
ax.plot([4.0, 4.0], [4.0, 5.8], color='gray', linewidth=2, linestyle='-')

# Thermal anchoring note
ax.text(5.3, 2.0, 'Cables thermally\nanchored at\neach stage', fontsize=8, ha='center',
        bbox=dict(boxstyle='round', facecolor='white', edgecolor='gray', alpha=0.8))

# === KEY METRICS BOX ===
metrics_text = """Key System Parameters:
• Chip dissipation: ~1-100 mW
• Production model: 5 K / 400 W/W
• I/O heat load: ~µW per wire
• 4K cooling capacity: ~1-10 W"""

ax.text(0.3, 0.2, metrics_text, fontsize=9, fontfamily='monospace',
        bbox=dict(boxstyle='round', facecolor='white', edgecolor='black', alpha=0.9),
        verticalalignment='bottom')

# Title
ax.set_title('SCE System Architecture: Cryogenic Integration', fontsize=14, fontweight='bold', pad=10)

plt.tight_layout()
plt.show()

print("The thermal boundary is where the I/O challenge lives:")
print("- Every physical data path adds heat to the cold stage")
print("- Cables are thermally anchored at intermediate and cold stages")
print("- High arithmetic intensity minimizes data crossing the boundary")

# Visualize: SCE System Architecture fig, ax = plt.subplots(figsize=(14, 8)) ax.set_xlim(0, 16) ax.set_ylim(0, 10) ax.axis('off') # Color scheme for temperature zones colors_temp = { '40K': '#ffe0cc', # orange 'cold': '#cce5ff', # cold blue } # === CRYOSTAT (center) === # Cryostat vacuum vessel (outer boundary) - narrower to leave room for external components cryostat = FancyBboxPatch((4, 0.5), 7, 9, boxstyle="round,pad=0.05", facecolor='#f0f0f0', edgecolor='black', linewidth=3) ax.add_patch(cryostat) ax.text(7.5, 9.7, 'Cryostat (vacuum)', ha='center', fontsize=12, fontweight='bold') # 40K - Intermediate stage (radiation shield) stage_40k = FancyBboxPatch((4.5, 1), 6, 7.5, boxstyle="round,pad=0.05", facecolor=colors_temp['40K'], edgecolor='black', linewidth=2) ax.add_patch(stage_40k) ax.text(7.5, 8.7, '40K Stage', ha='center', fontsize=10, fontweight='bold') # Cold stage (innermost): 4 K bench, 5 K production model stage_4k = FancyBboxPatch((5, 1.5), 5, 6, boxstyle="round,pad=0.05", facecolor=colors_temp['cold'], edgecolor='black', linewidth=2) ax.add_patch(stage_4k) ax.text(7.5, 7.7, '4–5 K Stage', ha='center', fontsize=10, fontweight='bold', color=COLORS['primary']) # SCE chip at the cold stage chip = FancyBboxPatch((5.5, 3), 4, 3, boxstyle="round,pad=0.02", facecolor=COLORS['sce'], edgecolor='black', linewidth=2, alpha=0.8) ax.add_patch(chip) ax.text(7.5, 4.5, 'AQFP\nProcessor', ha='center', va='center', fontsize=12, fontweight='bold', color='white') ax.text(7.5, 3.2, '~mW dissipation', ha='center', fontsize=9, color='white') # === COLD HEAD (outside cryostat, connected via flange) === cryo_head = FancyBboxPatch((11.5, 3), 1.8, 4, boxstyle="round,pad=0.03", facecolor='#c0c0c0', edgecolor='black', linewidth=2) ax.add_patch(cryo_head) ax.text(12.4, 6.3, 'Cold\nHead', ha='center', fontsize=9, fontweight='bold') ax.text(12.4, 4.5, 'GM/Pulse\nTube', ha='center', fontsize=8) # Cold finger penetrating into cryostat ax.plot([11, 11.5], [5, 5], color='#c0c0c0', linewidth=8, solid_capstyle='butt') ax.plot([11, 11.5], [5, 5], color='black', linewidth=10, solid_capstyle='butt', alpha=0.3) ax.text(10.5, 5.5, 'Cold\nfinger', fontsize=7, ha='center') # === COMPRESSOR (external, bottom right) === compressor = FancyBboxPatch((12.5, 0.5), 3, 1.8, boxstyle="round,pad=0.02", facecolor='#e0e0e0', edgecolor='black', linewidth=2) ax.add_patch(compressor) ax.text(14, 1.4, 'Compressor', ha='center', fontsize=10, fontweight='bold') ax.text(14, 0.9, '~1-10 kW (room temp)', ha='center', fontsize=8, color=COLORS['danger']) # Helium lines connecting compressor to cold head ax.annotate('', xy=(12.4, 2.9), xytext=(13.2, 2.4), arrowprops=dict(arrowstyle='-', color='gray', lw=3, connectionstyle='arc3,rad=-0.2')) ax.annotate('', xy=(12.4, 3.1), xytext=(14.5, 2.4), arrowprops=dict(arrowstyle='-', color='gray', lw=3, connectionstyle='arc3,rad=0.2')) ax.text(13.8, 2.6, 'He lines', fontsize=7, color='gray') # === HOST SYSTEM (left side, completely outside cryostat) === host = FancyBboxPatch((0.3, 2.5), 2.8, 5, boxstyle="round,pad=0.05", facecolor=COLORS['secondary'], edgecolor='black', linewidth=2, alpha=0.8) ax.add_patch(host) ax.text(1.7, 6.8, 'Room Temperature', ha='center', fontsize=10, fontweight='bold') ax.text(1.7, 5.5, 'Host System', ha='center', fontsize=11, fontweight='bold', color='white') ax.text(1.7, 4.5, 'CPU / GPU\nMemory\nNetwork', ha='center', fontsize=10, color='white') ax.text(1.7, 3.0, '300K', ha='center', fontsize=12, fontweight='bold', color='white') # === I/O CABLES (crossing into cryostat) === ax.annotate('', xy=(5.3, 4.8), xytext=(3.2, 4.8), arrowprops=dict(arrowstyle='->', color=COLORS['primary'], lw=3)) ax.annotate('', xy=(3.2, 4.2), xytext=(5.3, 4.2), arrowprops=dict(arrowstyle='->', color=COLORS['primary'], lw=3)) ax.text(3.6, 5.1, 'Data In', fontsize=9, color=COLORS['primary'], fontweight='bold') ax.text(3.6, 3.9, 'Data Out', fontsize=9, color=COLORS['primary'], fontweight='bold') # Feedthrough annotation ax.text(4.2, 6.2, 'Vacuum\nfeedthrough', fontsize=8, ha='center', bbox=dict(boxstyle='round', facecolor='white', edgecolor='gray', alpha=0.9)) ax.plot([4.0, 4.0], [4.0, 5.8], color='gray', linewidth=2, linestyle='-') # Thermal anchoring note ax.text(5.3, 2.0, 'Cables thermally\nanchored at\neach stage', fontsize=8, ha='center', bbox=dict(boxstyle='round', facecolor='white', edgecolor='gray', alpha=0.8)) # === KEY METRICS BOX === metrics_text = """Key System Parameters: • Chip dissipation: ~1-100 mW • Production model: 5 K / 400 W/W • I/O heat load: ~µW per wire • 4K cooling capacity: ~1-10 W""" ax.text(0.3, 0.2, metrics_text, fontsize=9, fontfamily='monospace', bbox=dict(boxstyle='round', facecolor='white', edgecolor='black', alpha=0.9), verticalalignment='bottom') # Title ax.set_title('SCE System Architecture: Cryogenic Integration', fontsize=14, fontweight='bold', pad=10) plt.tight_layout() plt.show() print("The thermal boundary is where the I/O challenge lives:") print("- Every physical data path adds heat to the cold stage") print("- Cables are thermally anchored at intermediate and cold stages") print("- High arithmetic intensity minimizes data crossing the boundary")

The thermal boundary is where the I/O challenge lives:
- Every physical data path adds heat to the cold stage
- Cables are thermally anchored at intermediate and cold stages
- High arithmetic intensity minimizes data crossing the boundary

---

3. Why AQFP?¶

---

Superconducting logic families make different trades among speed, bias distribution, event energy, and timing. This course emphasizes AQFP because its adiabatic operating mode supports very low dissipation and maps naturally to regular, deeply pipelined dataflow.

Logic-family context¶

Family	State or event	Bias and clock	Representative role
RSFQ	Quantized voltage pulse	Resistive DC bias plus clock/data pulses	Very high-speed digital logic
ERSFQ	Quantized voltage pulse	Inductive bias network	SFQ logic without resistive static bias
RQL	Reciprocal SFQ pulses	Multiphase AC clock	AC-powered high-throughput logic
AQFP	Circulating-current polarity	Multiphase AC excitation	Low-dissipation, deeply pipelined logic

Published AQFP hardware provides the 1.4 zJ/JJ-cycle reference. Representative SFQ event energies are roughly two orders of magnitude higher, but family-level device numbers do not determine a complete machine; clock networks, utilization, I/O, memory, and refrigeration must be included.

Adiabatic switching¶

1. The AC clock gradually changes a gate from a single-well to a bistable potential.
2. A weak input biases which stable state the circuit follows.
3. The device remains near a local energy minimum through the transition, limiting dissipation.
4. Slower transitions can reduce dissipation until throughput, noise, and operating margin set practical limits.

This description makes no assertion about clock-energy bookkeeping. The low-energy result comes from quasi-static device switching.

Architectural fit¶

• The AC excitation provides both timing and power to each stage.
• Gates evaluate in a deterministic phase order.
• State can be propagated or recirculated through clocked devices.
• Majority logic maps efficiently to arithmetic and regular dataflow.

System efficiency¶

The current static-inclusive production model uses 11.8–14.8× less wall energy than a host-inclusive B200, rounded to 12–15× in outward summaries. Its basis is 5 K, 400 W/W refrigeration, dense FP4 comparison, and the full routed clock fabric. The named packaged downside is 6.4–8.5× at 5 K/980 W/W; the central-plant upside is 15.7–19.5× at 5 K/207 W/W. These are modeled system results, not measurements of an integrated accelerator.

In [5]:

# Qualitative comparison of superconducting logic families
families = ['RSFQ', 'ERSFQ', 'RQL', 'AQFP']
attributes = ['Pulse event', 'Inductive DC bias', 'AC reciprocal pulses', 'Adiabatic state']
colors = [COLORS['danger'], COLORS['secondary'], COLORS['purple'], COLORS['sce']]

fig, ax = plt.subplots(figsize=(10, 4.8))
ax.axis('off')
table = ax.table(cellText=[[f, a] for f, a in zip(families, attributes)],
                 colLabels=['Family', 'Operating mode'], loc='center', cellLoc='left')
table.auto_set_font_size(False)
table.set_fontsize(12)
table.scale(1, 1.8)
for row, color in enumerate(colors, start=1):
    table[(row, 0)].set_facecolor(color)
    table[(row, 0)].set_text_props(color='white', fontweight='bold')
ax.set_title('Superconducting Logic Families', fontsize=14, fontweight='bold', pad=18)
plt.tight_layout()
plt.show()

print('Device event energy, clock distribution, utilization, I/O, memory, and refrigeration')
print('must be accounted for before comparing complete systems.')

# Qualitative comparison of superconducting logic families families = ['RSFQ', 'ERSFQ', 'RQL', 'AQFP'] attributes = ['Pulse event', 'Inductive DC bias', 'AC reciprocal pulses', 'Adiabatic state'] colors = [COLORS['danger'], COLORS['secondary'], COLORS['purple'], COLORS['sce']] fig, ax = plt.subplots(figsize=(10, 4.8)) ax.axis('off') table = ax.table(cellText=[[f, a] for f, a in zip(families, attributes)], colLabels=['Family', 'Operating mode'], loc='center', cellLoc='left') table.auto_set_font_size(False) table.set_fontsize(12) table.scale(1, 1.8) for row, color in enumerate(colors, start=1): table[(row, 0)].set_facecolor(color) table[(row, 0)].set_text_props(color='white', fontweight='bold') ax.set_title('Superconducting Logic Families', fontsize=14, fontweight='bold', pad=18) plt.tight_layout() plt.show() print('Device event energy, clock distribution, utilization, I/O, memory, and refrigeration') print('must be accounted for before comparing complete systems.')

Device event energy, clock distribution, utilization, I/O, memory, and refrigeration
must be accounted for before comparing complete systems.

---

4. Where SCE Fits¶

---

SCE is most attractive when the workload and deployment can amortize refrigeration and boundary traffic.

High-reuse computation¶

• Batched matrix multiplication and convolution reuse weights or activations across many operations.
• Regular pipelines keep a wide fabric occupied despite deep stage latency.
• Predictable access patterns allow state to remain in local registers or recirculation paths.

Cryogenic instruments¶

Quantum-control, radio-astronomy, and biomagnetic systems already contain cold stages. Their existing cryogenic infrastructure can reduce the incremental integration burden, but it does not make refrigeration free: added device and I/O heat still consumes finite cold-stage capacity.

Workload-screening questions¶

Question	Favorable answer
Can operands be reused many times?	Yes; boundary traffic is amortized
Can work be pipelined and parallelized?	Yes; deep stages remain occupied
Is throughput more important than single-item latency?	Yes; latency can be hidden across streams
Can warm-memory traffic be bounded?	Yes; I/O does not erase device headroom
Does the installation justify a refrigerator?	Yes; system overhead has useful work to serve

These are screening criteria, not guarantees. A full comparison still needs workload execution, utilization, I/O, memory, static load, and refrigerator performance.

In [6]:

# Visualize: Application fit matrix
fig, ax = plt.subplots(figsize=(12, 7))

# (name, compute_fit, memory_fit, size, label_offset_x, label_offset_y)
applications = [
    ('LLM Inference', 0.95, 0.9, 100, 5, -15),
    ('Vision/Diffusion', 0.9, 0.85, 80, 5, 8),
    ('Quantum Control', 0.95, 0.85, 60, -90, 5),
    ('HPC (Weather)', 0.75, 0.7, 60, 5, 5),
    ('Signal Processing', 0.7, 0.75, 50, 5, 5),
    ('AI Training', 0.5, 0.6, 90, 5, 5),
    ('General CPU', 0.2, 0.3, 50, 5, 5),
    ('Mobile/Edge', 0.1, 0.1, 30, 5, 5),
]

for name, compute_fit, memory_fit, size, off_x, off_y in applications:
    color = COLORS['sce'] if compute_fit > 0.6 and memory_fit > 0.6 else COLORS['secondary'] if compute_fit > 0.4 or memory_fit > 0.4 else COLORS['cmos']
    ax.scatter(memory_fit, compute_fit, s=size*10, c=color, alpha=0.7, edgecolors='black', linewidth=1.5)
    ax.annotate(name, (memory_fit, compute_fit), xytext=(off_x, off_y), textcoords='offset points', fontsize=9)

# Quadrant lines
ax.axhline(y=0.6, color='gray', linestyle='--', alpha=0.5)
ax.axvline(x=0.6, color='gray', linestyle='--', alpha=0.5)

# Quadrant labels
ax.text(0.8, 0.98, 'IDEAL FOR SCE', fontsize=12, fontweight='bold', color=COLORS['sce'], ha='center')
ax.text(0.3, 0.95, 'Compute OK,\nMemory Challenge', fontsize=9, ha='center', color=COLORS['secondary'])
ax.text(0.8, 0.2, 'Memory OK,\nCompute Challenge', fontsize=9, ha='center', color=COLORS['secondary'])
ax.text(0.3, 0.2, 'NOT SUITABLE', fontsize=10, fontweight='bold', ha='center', color=COLORS['cmos'])

ax.set_xlabel('Memory Access Predictability', fontsize=11)
ax.set_ylabel('Compute Density Fit', fontsize=11)
ax.set_title('Application Suitability for SCE', fontsize=14, fontweight='bold')
ax.set_xlim(0, 1)
ax.set_ylim(0, 1)

plt.tight_layout()
plt.show()

print("Existing cryogenic infrastructure changes the integration boundary, but device heat still adds refrigerator load.")

# Visualize: Application fit matrix fig, ax = plt.subplots(figsize=(12, 7)) # (name, compute_fit, memory_fit, size, label_offset_x, label_offset_y) applications = [ ('LLM Inference', 0.95, 0.9, 100, 5, -15), ('Vision/Diffusion', 0.9, 0.85, 80, 5, 8), ('Quantum Control', 0.95, 0.85, 60, -90, 5), ('HPC (Weather)', 0.75, 0.7, 60, 5, 5), ('Signal Processing', 0.7, 0.75, 50, 5, 5), ('AI Training', 0.5, 0.6, 90, 5, 5), ('General CPU', 0.2, 0.3, 50, 5, 5), ('Mobile/Edge', 0.1, 0.1, 30, 5, 5), ] for name, compute_fit, memory_fit, size, off_x, off_y in applications: color = COLORS['sce'] if compute_fit > 0.6 and memory_fit > 0.6 else COLORS['secondary'] if compute_fit > 0.4 or memory_fit > 0.4 else COLORS['cmos'] ax.scatter(memory_fit, compute_fit, s=size*10, c=color, alpha=0.7, edgecolors='black', linewidth=1.5) ax.annotate(name, (memory_fit, compute_fit), xytext=(off_x, off_y), textcoords='offset points', fontsize=9) # Quadrant lines ax.axhline(y=0.6, color='gray', linestyle='--', alpha=0.5) ax.axvline(x=0.6, color='gray', linestyle='--', alpha=0.5) # Quadrant labels ax.text(0.8, 0.98, 'IDEAL FOR SCE', fontsize=12, fontweight='bold', color=COLORS['sce'], ha='center') ax.text(0.3, 0.95, 'Compute OK,\nMemory Challenge', fontsize=9, ha='center', color=COLORS['secondary']) ax.text(0.8, 0.2, 'Memory OK,\nCompute Challenge', fontsize=9, ha='center', color=COLORS['secondary']) ax.text(0.3, 0.2, 'NOT SUITABLE', fontsize=10, fontweight='bold', ha='center', color=COLORS['cmos']) ax.set_xlabel('Memory Access Predictability', fontsize=11) ax.set_ylabel('Compute Density Fit', fontsize=11) ax.set_title('Application Suitability for SCE', fontsize=14, fontweight='bold') ax.set_xlim(0, 1) ax.set_ylim(0, 1) plt.tight_layout() plt.show() print("Existing cryogenic infrastructure changes the integration boundary, but device heat still adds refrigerator load.")

Existing cryogenic infrastructure changes the integration boundary, but device heat still adds refrigerator load.

---

5. Limits of the Fit¶

---

SCE is a poor match when the refrigerator, boundary traffic, or pipeline structure dominates the useful work.

Mobile and intermittently used systems¶

Phones and laptops cannot support the mass, power, acoustic, and maintenance envelope of a cryogenic refrigerator. Short, sporadic workloads also provide little time to amortize cooldown and static system load.

Branch-heavy and low-reuse work¶

Irregular control flow, pointer chasing, and frequent random access leave a deeply pipelined fabric underused. A heterogeneous system can retain conventional CPUs for orchestration while assigning regular kernels to a specialized accelerator.

Practical boundary¶

Factor	Present constraint
Form factor	Rack or instrument scale
Workload flexibility	Specialized dataflow rather than general single-thread execution
Ecosystem	Young design, verification, packaging, and software tooling
Fabrication	Mature optical dimensions but specialized superconducting processes

The fit depends on useful throughput per wall joule under a stated workload, not on device energy alone.

---

6. Open Engineering Problems¶

---

Thermal budget¶

Cold-stage heat must include switching, clock-distribution loss, wiring, optical or electrical I/O, static cryostat load, and any cold analog electronics. Refrigerator W/W varies strongly with temperature and machine scale; a single universal multiplier is not adequate.

Memory hierarchy¶

Warm memory retains capacity and density advantages, while repeated thermal-boundary traffic costs energy. Useful architectures exploit local registers, recirculation, batching, and algorithmic reuse before paying for another warm-memory access.

I/O bandwidth¶

Electrical wiring conducts heat and requires controlled return paths. Optical ingress can reduce conductive heat and provide galvanic isolation, but receiver heat, source energy, alignment, and packaging remain part of the budget.

Circuit design¶

AQFP combines small data signals, a larger excitation field, explicit fanout, multiphase timing, and inductive coupling. Simulation and layout verification must therefore include electromagnetic geometry and clock-data interaction.

Fabrication and scale¶

Superconducting foundries have demonstrated large operating circuits, but useful accelerator scale also depends on design margin, flux control, clock distribution, packaging, and repeatable test. Process yield and design yield must be measured separately.

In [7]:

# Visualize: Challenge/Opportunity matrix
fig, ax = plt.subplots(figsize=(12, 7))

challenges = [
    ('Thermal budget scaling', 'Medium', 'Medium', 'Cryo is mature; question is compute density'),
    ('Memory hierarchy', 'Medium', 'High', 'Solved for LLM inference'),
    ('I/O bandwidth', 'Low', 'Low', 'Active research area'),
    ('Circuit design constraints', 'Medium', 'Medium', 'Specialized architectures (AM) address constraints'),
    ('Fab maturity', 'High', 'High', 'Multiple fabs now available'),
    ('Soft defects (trapped flux)', 'High', 'High', 'Field control, moats, and cooldown protocol'),
]

# Create table
ax.axis('off')
table_data = [['Challenge', 'Difficulty', 'Progress', 'Notes']] + \
             [[c[0], c[1], c[2], c[3]] for c in challenges]

# Separate color maps for Difficulty (high=bad) and Progress (high=good)
difficulty_colors = {
    'High': COLORS['danger'],      # Red = hard
    'Medium': COLORS['secondary'], # Orange = medium
    'Low': COLORS['success'],      # Green = easy
}
progress_colors = {
    'High': COLORS['success'],     # Green = good progress
    'Medium': COLORS['secondary'], # Orange = medium
    'Low': COLORS['danger'],       # Red = little progress
}

table = ax.table(cellText=table_data, loc='center', cellLoc='center',
                 colWidths=[0.25, 0.15, 0.15, 0.4])
table.auto_set_font_size(False)
table.set_fontsize(10)
table.scale(1, 2)

# Style header
for j in range(4):
    table[(0, j)].set_facecolor(COLORS['dark'])
    table[(0, j)].set_text_props(color='white', fontweight='bold')

# Style cells with appropriate color semantics
for i in range(1, len(table_data)):
    diff = table_data[i][1]
    prog = table_data[i][2]
    # Difficulty column
    table[(i, 1)].set_facecolor(difficulty_colors.get(diff, 'white'))
    table[(i, 1)].set_text_props(color='white' if diff == 'High' else 'black')
    # Progress column (inverted semantics)
    table[(i, 2)].set_facecolor(progress_colors.get(prog, 'white'))
    table[(i, 2)].set_text_props(color='white' if prog == 'Low' else 'black')

ax.set_title('Open Problems: Difficulty vs Progress', fontsize=14, fontweight='bold', pad=20)

plt.tight_layout()
plt.show()

print("\nKey insight: Most challenges are engineering problems, not fundamental physics barriers.")

# Visualize: Challenge/Opportunity matrix fig, ax = plt.subplots(figsize=(12, 7)) challenges = [ ('Thermal budget scaling', 'Medium', 'Medium', 'Cryo is mature; question is compute density'), ('Memory hierarchy', 'Medium', 'High', 'Solved for LLM inference'), ('I/O bandwidth', 'Low', 'Low', 'Active research area'), ('Circuit design constraints', 'Medium', 'Medium', 'Specialized architectures (AM) address constraints'), ('Fab maturity', 'High', 'High', 'Multiple fabs now available'), ('Soft defects (trapped flux)', 'High', 'High', 'Field control, moats, and cooldown protocol'), ] # Create table ax.axis('off') table_data = [['Challenge', 'Difficulty', 'Progress', 'Notes']] + \ [[c[0], c[1], c[2], c[3]] for c in challenges] # Separate color maps for Difficulty (high=bad) and Progress (high=good) difficulty_colors = { 'High': COLORS['danger'], # Red = hard 'Medium': COLORS['secondary'], # Orange = medium 'Low': COLORS['success'], # Green = easy } progress_colors = { 'High': COLORS['success'], # Green = good progress 'Medium': COLORS['secondary'], # Orange = medium 'Low': COLORS['danger'], # Red = little progress } table = ax.table(cellText=table_data, loc='center', cellLoc='center', colWidths=[0.25, 0.15, 0.15, 0.4]) table.auto_set_font_size(False) table.set_fontsize(10) table.scale(1, 2) # Style header for j in range(4): table[(0, j)].set_facecolor(COLORS['dark']) table[(0, j)].set_text_props(color='white', fontweight='bold') # Style cells with appropriate color semantics for i in range(1, len(table_data)): diff = table_data[i][1] prog = table_data[i][2] # Difficulty column table[(i, 1)].set_facecolor(difficulty_colors.get(diff, 'white')) table[(i, 1)].set_text_props(color='white' if diff == 'High' else 'black') # Progress column (inverted semantics) table[(i, 2)].set_facecolor(progress_colors.get(prog, 'white')) table[(i, 2)].set_text_props(color='white' if prog == 'Low' else 'black') ax.set_title('Open Problems: Difficulty vs Progress', fontsize=14, fontweight='bold', pad=20) plt.tight_layout() plt.show() print("\nKey insight: Most challenges are engineering problems, not fundamental physics barriers.")

Key insight: Most challenges are engineering problems, not fundamental physics barriers.

---

7. The Path Forward¶

---

Why the question is timely¶

AI has made energy, memory bandwidth, and power delivery first-order architecture constraints. At the same time, superconducting circuit processes, cryogenic components, and design tools provide enough maturity to test complete device-to-system hypotheses rather than isolated gates.

Research landscape¶

The literature spans metrology and sensors, SFQ digital systems, AQFP logic, superconducting fabrication, cryogenic control, and optical interfaces. Representative institutional lineages include NIST for standards, MIT Lincoln Laboratory for superconducting processes and circuits, and Yokohama National University with AIST for AQFP devices and the MANA processor. Organization names and commercial offerings change; the course relies on primary publications for technical results.

Evidence ladder¶

Stage	Question
Device	Does fabricated hardware match the energy and margin model?
Block	Do arithmetic, storage, and clock structures operate together?
Chip	Does routed scale preserve timing, field tolerance, and yield?
System	Do I/O, memory, refrigeration, and utilization preserve wall-energy benefit?
Workload	Does a real model run at the promised accuracy, throughput, and energy?

This course follows the same order: physics, devices, circuits, integration, and architecture.

In [8]:

# Visualize: Technology adoption and field maturity
fig, ax = plt.subplots(figsize=(10, 5))

# Technology maturity S-curve
x = np.linspace(0, 10, 100)
adoption = 100 / (1 + np.exp(-1.5*(x - 5)))  # S-curve

ax.plot(x, adoption, color=COLORS['sce'], linewidth=3)
ax.axvline(x=3, color='gray', linestyle='--', alpha=0.5)
ax.axvline(x=5, color='gray', linestyle='--', alpha=0.5)
ax.axvline(x=7, color='gray', linestyle='--', alpha=0.5)

ax.text(1.5, 85, 'Research', ha='center', fontsize=10)
ax.text(4, 85, 'Early\nDevelopment', ha='center', fontsize=10)
ax.text(6, 85, 'Deployment', ha='center', fontsize=10)
ax.text(8.5, 85, 'Maturity', ha='center', fontsize=10)

# SCE position - early development phase
sce_x = 4.0
sce_y = 100 / (1 + np.exp(-1.5*(sce_x - 5)))
ax.scatter([sce_x], [sce_y], s=200, color=COLORS['secondary'], zorder=5, edgecolors='black', linewidth=2)
ax.text(sce_x + 0.3, sce_y + 8, 'SCE is here', fontsize=10, fontweight='bold')

ax.set_xlabel('Field Development', fontsize=11)
ax.set_ylabel('Technology Maturity (%)', fontsize=11)
ax.set_title('SCE technology maturity and remaining development', fontsize=12, fontweight='bold')
ax.set_xlim(0, 10)
ax.set_ylim(0, 100)

plt.tight_layout()
plt.show()

print("Early-stage fields pair open technical questions with substantial uncertainty.")

# Visualize: Technology adoption and field maturity fig, ax = plt.subplots(figsize=(10, 5)) # Technology maturity S-curve x = np.linspace(0, 10, 100) adoption = 100 / (1 + np.exp(-1.5*(x - 5))) # S-curve ax.plot(x, adoption, color=COLORS['sce'], linewidth=3) ax.axvline(x=3, color='gray', linestyle='--', alpha=0.5) ax.axvline(x=5, color='gray', linestyle='--', alpha=0.5) ax.axvline(x=7, color='gray', linestyle='--', alpha=0.5) ax.text(1.5, 85, 'Research', ha='center', fontsize=10) ax.text(4, 85, 'Early\nDevelopment', ha='center', fontsize=10) ax.text(6, 85, 'Deployment', ha='center', fontsize=10) ax.text(8.5, 85, 'Maturity', ha='center', fontsize=10) # SCE position - early development phase sce_x = 4.0 sce_y = 100 / (1 + np.exp(-1.5*(sce_x - 5))) ax.scatter([sce_x], [sce_y], s=200, color=COLORS['secondary'], zorder=5, edgecolors='black', linewidth=2) ax.text(sce_x + 0.3, sce_y + 8, 'SCE is here', fontsize=10, fontweight='bold') ax.set_xlabel('Field Development', fontsize=11) ax.set_ylabel('Technology Maturity (%)', fontsize=11) ax.set_title('SCE technology maturity and remaining development', fontsize=12, fontweight='bold') ax.set_xlim(0, 10) ax.set_ylim(0, 100) plt.tight_layout() plt.show() print("Early-stage fields pair open technical questions with substantial uncertainty.")

Early-stage fields pair open technical questions with substantial uncertainty.

---

Summary¶

---

Question	Course answer
What is SCE?	Electronics built from superconducting devices, interconnect, and quantum phase effects
Why AQFP?	Quasi-static switching has measured very low dissipation at the device
What is measured?	1.4 zJ per Josephson junction per cycle in published hardware at 4.2 K and 5 GHz
What is modeled?	11.8–14.8× less wall energy at the 5 K/400 W/W production point against a host-inclusive B200
Which workloads fit?	Regular, parallel, high-reuse work with bounded warm-cold traffic
What remains?	Scale, clocking, I/O, memory, refrigeration, utilization, fabrication, and integrated measurement

The course develops the physics and engineering needed to evaluate each link in that chain.

---

Check Your Understanding¶

1. At 4.2 K, compute $k_B T\ln 2$ and compare it with the measured 1.4 zJ/JJ-cycle AQFP reference. What does the ratio describe, and what does it omit?
2. A workload performs one off-chip read for every MAC. Which system term is likely to dominate even if device switching is near the thermodynamic limit?
3. Classify each statement as measured, modeled, or targeted: 1.4 zJ/JJ-cycle at 4.2 K; 11.8–14.8× less wall energy at 5 K/400 W/W; 5 GHz for a future production accelerator.

Lecture 0 complete
The opportunity begins at the device and survives only through disciplined system accounting.

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